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march 2009 rev 2 1/25 25 L6562AT transition-mode pfc controller features guaranteed for extreme temperature range (outdoor) proprietary multiplier design for minimum thd very accurate adjustable output overvoltage protection ultra-low (30 a) start-up current low (2.5 ma) quiescent current digital leading-edge blanking on current sense disable function on e/a input 1% (@ t j = 25 c) internal reference voltage -600/+800 ma totem pole gate driver with active pull-down during uvlo and voltage clamp dip-8/so-8 packages applications pfc pre-regulators for: street lighting iec61000-3-2 compliant smps (flat tv, monitors, desktop pc, games) electronic ballast so-8 dip-8 figure 1. block diagram table 1. device summary order codes package packaging L6562ATn dip-8 tube L6562ATd so-8 tu b e L6562ATdtr tape and reel www.st.com
contents L6562AT 2/25 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 typical electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3 thd optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4 operating with no auxiliary winding on the boost inductor . . . . . . . . . . . . 15 7.5 comparison between the L6562AT and the l6562 . . . . . . . . . . . . . . . . . 16 8 application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
description L6562AT 3/25 1 description the L6562AT is a current-mode pfc controller operating in transition mode (tm). coming with the same pin-out as its predecessors l6561 and l6562, it offers improved performance. the highly linear multiplier includes a specia l circuit, able to reduce ac input current distortion, that allows wide-range-mains operation with an extremely low thd, even over a large load range. the output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @t j = 25 c) internal voltage reference. the device features extremely low consumption (60 a max. before start-up and < 5.5 ma operating) and includes a disable function suitable for ic remote on/off, which makes it easier to comply with energy saving requirements (blue angel, energystar, energy2000, etc.). an effective two-step ovp enables to safely handle over-voltages either occurring at start- up or resulting from load disconnection. the totem-pole output stage, capable of 600 ma source and 800 ma sink current, is suitable to drive high current mosfets or igbts. this, combined with the other features and the possibility to operate with the proprietary fixed-off-time c ontrol, makes the device an excellent low-cost solution for en61000-3-2 compliant smps in excess of 350 w.
pin settings L6562AT 4/25 2 pin settings 2.1 pin connection figure 2. pin connection (top view) 2.2 pin description zcd inv comp mult cs vcc gd gnd 1 2 3 4 8 7 6 5 table 2. pin description pin n name description 1inv inverting input of the error amplifier. the information on the output voltage of the pfc pre-regulator is fed into this pin through a resistor divider. the pin doubles as an on/off control input. 2comp output of the error amplifier. a com pensation network is placed between this pin and inv to achieve stability of the voltage control loop and ensure high power factor and low thd. 3mult main input to the multiplier. this pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. 4cs input to the pwm comparator. the curre nt flowing in the mosfet is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine mosfet?s turn-off. the pin is equipped with 200 ns leading-edge blanking for improved noise immunity. 5zcd boost inductor?s demagnetization sensing input for transition-mode operation. a negative-going edge triggers mosfet?s turn-on. 6 gnd ground. current return for both the sig nal part of the ic and the gate driver. 7gd gate driver output. the totem pole output stage is able to drive power mosfet?s and igbt?s with a peak curr ent of 600 ma source and 800 ma sink. the high-level voltage of this pi n is clamped at about 12 v to avoid excessive gate voltages in case the pin is supplied with a high vcc. 8vcc supply voltage of both the signal part of the ic and the gate driver. the supply voltage upper limit is extended to 22 v min. to provide more headroom for supply voltage changes.
maximum ratings L6562AT 5/25 3 maximum ratings 4 thermal data table 3. absolute maximum ratings symbol pin parameter value unit v cc 8 ic supply voltage (i cc 20 ma) self-limited v i gd 7 output totem pole peak current self-limited a --- 1 to 4 analog inputs and outputs -0.3 to 8 v i zcd 5 zero current detecto r max. current 10 ma table 4. thermal data symbol parameter value unit so8 dip8 r thja max. thermal resist ance, junction-to- ambient 150 100 c/w p tot power dissipation @t a = 50 c 0.65 1 w t j junction temperature operating range -40 to 150 c t stg storage temperature -55 to 150 c
electrical characteristics L6562AT 6/25 5 electrical characteristics -40 c < t j < +125 c, v cc = 12 v, c o = 1 nf; unless otherwise specified table 5. electrical characteristics symbol parameter test condition min typ max unit supply voltage v cc operating range after turn-on 10.5 22.5 v vcc on turn-on threshold (1) 11.7 12.5 13.3 v vcc off turn-off threshold (1) 9.5 10 10.5 v hys hysteresis 2.2 2.8 v v z zener voltage i cc = 20 ma 22.5 25 28 v supply current i start-up start-up current before turn-on, v cc = 11 v 30 60 a i q quiescent current after turn-on 2.5 3.9 ma i cc operating supply current @ 70 khz 3.5 5.5 ma i q quiescent current during ovp (either static or dynamic) or v inv 150 mv 1.7 2.2 ma multiplier input i mult input bias current v mult = 0 to 4 v -1 a v mult linear operation range 0 to 3 v output max. slope v mult = 0 to 1 v, v comp = upper clamp 11.1 v/v k gain (2) v mult = 1 v, v comp = 4 v, 0.32 0.38 0.47 v error amplifier v inv voltage feedback input threshold t j = 25 c 2.475 2.5 2.525 v 10.5 v < v cc < 22.5 v (1) 2.44 2.545 line regulation v cc = 10.5 v to 22.5 v 2 5 mv i inv input bias current v inv = 0 to 3 v -1 a gv voltage gain open loop 60 80 db gb gain-bandwidth product 1 mhz i comp source current v comp = 4 v, v inv = 2.4 v -2 -3.5 -5 ma sink current v comp = 4 v, v inv = 2.6 v 2.5 4.5 ma v comp upper clamp voltage i source = 0.5 ma 5.1 5.7 6 v lower clamp voltage i sink = 0.5 ma (1) 2.12.252.4 v v invdis disable threshold 150 200 250 mv v inven restart threshold 380 450 520 mv v cs v mult ---------------------
electrical characteristics L6562AT 7/25 symbol parameter test condition min typ max unit output overvoltage i ovp dynamic ovp triggering current 19.5 27 30.5 a hys hysteresis (3) 20 a static ovp threshold (1) 2.12.252.4 v current sense comparator i cs input bias current v cs = 0 -1 a t leb leading edge blanking 100 200 300 ns td (h-l) delay to output 175 ns v cs current sense clamp v comp = upper clamp, vmult = 1.5 v 1.0 1.08 1.16 v vcs offset current sense offset v mult = 0 25 mv v mult = 2.5 v 5 zero current detector v zcdh upper clamp voltage i zcd = 2.5 ma 5.0 5.7 6.5 v v zcdl lower clamp voltage i zcd = - 2.5 ma -0.5 0 0.5 v v zcda arming voltage (positive-going edge) (3) 1.4 v v zcdt triggering voltage (negative-going edge) (3) 0.7 v i zcdb input bias current v zcd = 1 to 4.5 v 2 a i zcdsrc source current capability -1.5 ma i zcdsnk sink current capability 1.5 ma starter t start start timer period 75 190 300 s gate driver v ol output low voltage i sink = 100 ma 0.6 1.2 v v oh output high voltage i source = 5 ma 9.5 10.3 v i srcpk peak source current -0.6 a i snkpk peak sink current 0.8 a t f voltage fall time 30 70 ns t r voltage rise time 60 130 ns v oclamp output clamp voltage i source = 5 ma; vcc = 20 v 10 12 15 v uvlo saturation vcc = 0 to v ccon , i sink = 2 ma 1.1 v 1. all the parameters are in tracking 2. the multiplier output is given by: 3. parameters guaranteed by design, functionality tested in production. table 5. electrical characteristics (continued) ( ) 5 . 2 v v k v comp mult cs ? ? = ?
typical electrical characteristic L6562AT 8/25 6 typical electrical characteristic figure 3. supply current vs supply voltage figure 4. start-up and uvlo vs t j figure 5. ic consumption vs t j figure 6. vcc zener voltage vs t j 0.00 0.01 0.10 1.00 10.00 0.00 5.00 10.00 15.00 20.00 25.00 vcc (v) icc (ma) co = 1 nf f = 70 khz tj = 25c pj 9 10 11 12 13 -50 0 50 100 150 tj (c) (v) vcc-on vcc-off pj 0.01 0.1 1 10 -50 0 50 100 150 tj (c) icc (ma) before start-up disabled or during ovp quiescent ope r ating vcc = 12 v co= 1 nf f = 70 khz 22 23 24 25 26 27 28 -50 0 50 100 150 tj (c) vccz (v)
typical electrical characteristic L6562AT 9/25 figure 7. feedback reference vs t j figure 8. ovp current vs t j figure 9. e/a output clamp levels vs t j figure 10. delay-to-output vs t j 2.4 2.45 2.5 2.55 2.6 -50 0 50 100 150 tj (c) vref (v) vcc = 12v j 23 24 25 26 27 28 29 30 31 32 33 34 35 -50 0 50 100 150 tj (c) iovp (ua) vcc = 12v 1 2 3 4 5 6 -50 0 50 100 150 tj (c) v comp pin2 (v) vcc = 12v upper clamp lower clamp 0 100 200 300 -50 0 50 100 150 tj (c) td (h-l) (ns) vcc = 12v
typical electrical characteristic L6562AT 10/25 figure 11. multiplier characteristic figure 12. vcs clamp vs t j figure 13. zcd clamp levels vs t j figure 14. start-up timer vs t j p -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 vmult (pin3) (v) vcs (pin4) (v) v comp (pin2) (v ) upper volt. clamp 2.5 v 3 v 3.5v 4 v 5.75 v 4.5v 5 v 1 1.1 1.2 1.3 -50 0 50 100 150 tj (c) vcsx (v) vcc = 12v vcomp = upper clamp pj -1 0 1 2 3 4 5 6 7 -50 0 50 100 150 tj (c) vzcd (v) vcc = 12v izcd = 2.5 ma upper clamp lower clamp pj 150 160 170 180 190 200 -50 0 50 100 150 tj (c) tstart (us) vcc = 12v
typical electrical characteristic L6562AT 11/25 figure 15. gate-driver output low saturation figure 16. gate-drive output high saturation figure 17. gate-drive clamp vs t j figure 18. output gate drive low saturation vs t j during uvlo 0.00 1.00 2.00 3.00 4.00 5.00 0 200 400 600 800 1000 i gd (m a) vpin7 (v) tj = 25 c vcc = 12v sink 6.00 7.00 8.00 9.00 10.00 11.00 12.00 0 200 400 600 i gd (ma) vpin7 (v) tj = 25 c vcc = 12v source 12.5 12.75 13 13.25 13.5 -50 0 50 100 150 tj (c) vpin7 clamp (v) vcc = 20v 0.5 0.6 0.7 0.8 0.9 1 1.1 -50 0 50 100 150 tj (c) vpin7 (v) isink = 2 ma vcc = 0v vcc = 11v
application information L6562AT 12/25 7 application information 7.1 overvoltage protection under steady-state conditions, the voltage control loop keeps the output voltage vo of a pfc pre-regulator close to its nominal value, se t by the resistors r1 and r2 of the output divider. neglecting ripple components, the current through r1, i r1 , equals that through r2, i r2 . considering that the non-inverting input of th e error amplifier is inte rnally referenced at 2.5 v, also the voltage at pin inv will be 2.5 v, then: equation 1 if the output voltage experiences an abrupt change vo > 0 due to a load drop, the voltage at pin inv will be kept at 2.5 v by the loca l feedback of the error amplifier, a network connected between pins inv and comp that in troduces a long time constant to achieve high pf (this is why vo can be large). as a result, the current through r2 will remain equal to 2.5/r2 but that th rough r1 will become: equation 2 the difference current i r1 =i' r1 -i r2 =i' r1 -i r1 = vo/r1 will flow through the compensation network and enter the error amplifier output (p in comp). this curren t is monitored inside the device and if it reaches about 24 a the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy delivered to the ou tput. as the current exceeds 27 a, the ovp is triggered (dynamic o vp): the gate-drive is forced low to switch off the external power transistor and the ic put in an idle state. this co ndition is maintained until the current falls below approximately 7 a, which re-enables the internal starter and allows switching to restart. the output vo that is able to trigger the dynamic ovp function is then: equation 3 v o = r1 20 10 - 6 an important advantage of this technique is that the ov level can be set independently of the regulated output voltage: the latter depends on the ratio of r1 to r2, the former on the individual value of r1. another advantage is the precision: the tolerance of the detection current is 13%, i.e. 13% tolerance on vo. since vo << vo, the tolerance on the absolute value will be prop ortionally reduced. example: vo = 400 v, vo = 40 v. then: r1 = 40 v/27 a 1.5 m ; r2 = 1.5 m 2.5/(400-2.5) = 9.43 k . the tolerance on the ovp level due to the L6562AT will be 400.13 = 5.3 v, that is 1.2 %. i r2 i r1 2.5 r2 ------- - v o 2.5 ? r1 --------------------- - === i ' r1 v o 2.5 ? v o + r1 --------------------------------------- - =
application information L6562AT 13/25 when the load of a pfc pre-regulator is very low, the output voltage tends to stay steadily above the nominal value, which cannot be handled by the dynamic ovp. if this occurs, however, the error amplifier ou tput will saturate low; hence, when this is detected the external power transistor is switched off and the ic put in an idle state (static ovp). normal operation is resumed as the error amplifier goes back into its linear region. as a result, the device will work in burst-mode, with a repetition rate that can be very low. when either ovp is activated the quiescent co nsumption of the ic is reduced to minimize the discharge of the vcc capacitor and increa se the hold-up capability of the ic supply system. 7.2 disable function the inv pin doubles its function as a not-latched ic disable: a voltage below 0.2 v shuts down the ic and reduces its consumption at a lower value. to restart the ic, the voltage on the pin must exceed 0.45 v. the main usage of this function is a remote on/off control input that can be driven by a pwm controller for power management purposes. however it also offers a certain degree of a dditional safety since it will ca use the ic to shutdown in case the lower resistor of the output divider is shorte d to ground or if the upper resistor is missing or fails open. 7.3 thd optimizer circuit the device is equipped with a special circ uit that reduces the conduction dead-angle occurring to the ac input curr ent near the zero-crossings of the line voltage (crossover distortion). in this way the thd (total harmon ic distortion) of the current is considerably reduced. a major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very lo w. this effect is magnified by the high- frequency filter capacitor placed after the br idge rectifier, which re tains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop.
application information L6562AT 14/25 figure 19. thd optimization: standard tm pfc controller (left side) and L6562AT (right side) to overcome this issue the circuit embedded in the device forces the pfc pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. this will resu lt in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequen cy filter capacitor after the bridge. the effect of the circuit is shown in figu re 2, where the key waveforms of a standard tm pfc controller are compared to those of the L6562AT. essentially, the circuit artificially increases th e on-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. this offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. to maximally benefit from the thd optimizer circ uit, the high-frequency filter capacitor after the bridge rectifier should be minimized, co mpatibly with emi filtering needs. a large capacitance, in fact, introduces a conduction dea d-angle of the ac input current in itself - even with an ideal energy transfer by the pfc pre-regulator - thus making the action of the optimizer circuit little effective. imains vdrain imains vdrain input current input current mosfet's drain voltage mosfet's drain voltage rectified mains voltage rectified mains voltage input current input current
application information L6562AT 15/25 7.4 operating with no auxiliar y winding on the boost inductor to generate the synchronization signal on the zcd pin, the typical approach requires the connection between the pin and an auxiliary winding of the boos t inductor through a limiting resistor. when the device is supplied by the ca scaded dc-dc converter, it is necessary to introduce a supplementary winding to t he pfc choke just to operate the zcd pin. another solution could be implemented by simply connecting the zcd pin to the drain of the power mosfet through an r-c network as shown in figure 3: in this way the high- frequency edges expe rienced by the drain will be transf erred to the zcd pin, hence arming and triggering the zcd comparator. also in this case the resistance value must be properly chosen to limit the current sourced/sunk by the zcd pin. in typical applications with output voltages around 400 v, recommended values for these components are 22 pf (or 33 pf) for c zcd and 330 k for r zcd . with these values proper operation is guaranteed even with few volts difference between the regulated output vo ltage and the peak input voltage figure 20. zcd pin synchronization without auxiliary winding l6562 a t c zcd r zcd 5 zcd
application information L6562AT 16/25 7.5 comparison between th e L6562AT and the l6562 the L6562AT is not a direct drop-in replacemen t of the l6562, even if both have the same pin-out. one function (disable) has been relocated. table 2 compares the two devices, i.e. those pa rameters that may result in different values of the external components. the parameters th at have the most signi ficant impact on the design, i.e. that definitely require external component changes when converting an l6562- based design to the L6562AT, are highlighted in bold. the lower value (-36%) for the clamp level of t he current sense reference voltage allows the use of a lower sense resistor for the same peak current, with a proportional reduction of the associated power dissipation. essentially, the advantage is the reduction of the power dissipated in a single point (hotspot), which is a considerable benefit in applications where heat removal is critical, e.g. in adapters en closed in a sealed plastic case. the lower value for the dynamic ovp triggering current allows th e use of a higher resistance value (+48%) for the upper resistor of the divider sensing the output voltage of the pfc stage (keeping the same overvoltage level) with no significant incr ease of noise sensitivit y. this reduction goes in favor of standby consumption in applications required to comply with energy saving regulations. table 6. L6562AT vs l6562 parameter l6562 L6562AT ic turn-on and turn-off thresholds (typ.) 12/9.5 v 12.5/10 v turn-off threshold spread (max.) 0.8 v 0.5 v ic consumption before start-up (max.) 70 ua 60 ua multiplier gain (typ.) 0.6 0.38 current sense reference clamp (typ.) 1.7 v 1.08 v current sense propagation delay (delay -to-output) (typ.) 200 ns 175 ns dynamic ovp triggering current (typ.) 40 a 27 a zcd arm/trigger/clamp thresholds (typ.) 2.1/1.4/0.7 v 1.4/0.7/0 v enable threshold (typ.) 0.3 v (1) 1. function located on pin 5 (zcd) 0.45 v (2) 2. function located on pin 1 (inv) gate-driver internal drop (max.) 2.6 v 2.2 v leading-edge blanking on current sense no yes reference voltage accuracy (overall) 2.4% 1.8%
application examples and ideas L6562AT 17/25 8 application examples and ideas figure 21. demonstration board wide-range mains: electrical schematic ntc 2.5 8 3 p1 w08 r1 1 m c1 0.22 f 630v r3 15 k c29 22 f 25v f1 4a/250v r4 270 k d8 1n4148 d2 1n5248b r14 100 c5 r6 47 k t1 5 6 l6562a 7 21 r7 33 q1 stp8nm50fp 4 r11 1m c6 47 f 450v vo=400v po=80w r10 0.68 0.25w r13b 82 k + - c4 100 nf c2 10nf d1 stth1l06 r50 - 22 k c3 - 2200 nf r2 1 m r5 270 k r9 0.68 0.25w r12 c23 150 nf boost inductor spec (itacoil e2543/e) e25x13x7 core, n67 ferrite 1.5 mm gap for 0.7 mh primary inductance primary: 102 turns 20x0.1 mm secondary: 10 turns 0.1 mm r13 15 k vac 88v to 264v 1m vcc mult zcd comp inv gnd cs gd 10 nf r8 47k r15 shorted ntc 2.5 8 3 p1 w08 r1 1 m c1 0.22 f 630v r3 15 k c29 22 f 25v f1 4a/250v r4 270 k d8 1n4148 d2 1n5248b r14 100 c5 r6 47 k t1 5 6 l6562a 7 21 r7 33 q1 stp8nm50fp 4 r11 1m c6 47 f 450v vo=400v po=80w r10 0.68 0.25w r13b 82 k + - c4 100 nf c2 10nf d1 stth1l06 r50 - 22 k c3 - 2200 nf r2 1 m r5 270 k r9 0.68 0.25w r12 c23 150 nf boost inductor spec (itacoil e2543/e) e25x13x7 core, n67 ferrite 1.5 mm gap for 0.7 mh primary inductance primary: 102 turns 20x0.1 mm secondary: 10 turns 0.1 mm r13 15 k vac 88v to 264v 1m vcc mult zcd comp inv gnd cs gd 10 nf r8 47k r15 shorted l6562a
application examples and ideas L6562AT 18/25 figure 22. l6562a 80w tm pfc evaluation board: compliance to en61000-3-2 standard figure 23. l6562a 80w tm pfc evaluation board: compliance to jeida-miti standard vin = 230 vac - 50 hz, pout = 80 w thd = 10.48%, pf = 0.973 vin = 100 vac - 50 hz, pout = 80 w thd = 3.18%, pf = 0.997 0. 0001 0.001 0.01 0. 1 1 1 3 5 7 9 111315171921232527293133353739 harmonic order (n) harmonic current (a) measurements @ 230vac ful l l oad en61000-3-2 cl as s d l i mit s 0. 0001 0.001 0.01 0. 1 1 1 3 5 7 9 111315171921232527293133353739 harmonic order (n) harmoni c current (a) measurement s @ 100vac full load jeida-miti cl ass d l imi t s figure 24. l6562a 80w tm pfc evaluation board: input current waveform @230 v-50 hz ? 80w load figure 25. l6562a 80w tm pfc evaluation board: input current waveform @100 v-50 hz ? 80 w load
application examples and ideas L6562AT 19/25 figure 26. l6562a 80w tm pfc evaluation board: power factor vs vin figure 27. l6562a 80w tm pfc evaluation board: thd vs vin 0.80 0.85 0.90 0.95 1.00 80 100 120 140 160 180 200 220 240 260 vin (vac) pf pout = 80w 0 2 4 6 8 10 12 80 100 120 140 160 180 200 220 240 260 vin (vac) thd (% ) pout = 80w figure 28. l6562a 80w tm pfc evaluation board: efficiency vs vin figure 29. l6562a 80w tm pfc evaluation board: static vout regulation vs vin 75 80 85 90 95 100 80 100 120 140 160 180 200 220 240 260 vin (vac) efficiency (%) pout = 80w 400 400.5 401 401.5 402 402.5 403 403.5 404 80 100 120 140 160 180 200 220 240 260 vin (vac) vout (vdc) pout = 80w
application examples and ideas L6562AT 20/25 figure 30. demonstration board evl6562a-400w, wide-range mains, fot 1 2 3 4 6 5 7 8 l6562a + r1 9 1k0 l2 res c2 0 330pf l1 cm-1. 5mh-5a l3 dm-51uh-6a c1 5 100pf c1 6 220pf r2 2 0r39-1w r1 5 820 c1 1 470nf/5 0v c1 2 47uf/50v r1 6 15k 1 2 j1 q2 stp12nm5 0fp c1 470nf-x2 d6 ll4148 r2 0 0r39-1w d5 bzx85-c15 r2 3 0r68w r1 1m5 d1 1n5406 1 2 3 4 5 d3 stth8r06 f1 8a/250v r3 180k c2 1 10nf r1 7 6r8 r3 4 10k r1 8 6r8 q3 bc857c r3 3 620k d7 ll4148 c4 470nf-630v r3 2 620k d8 ll4148 r2 ntc 2r5-s237 l4 pq40-500u h q1 stp12nm5 0fp r4 180k r3 1 1k5 r2 1 0r39-1w + - ~ ~ d2 d1 5xb6 0 r5 47r c5 470nf-630v r1 2 9.1k r1 1 680k r1 0 750k r3 5 3r9 r3 6 3r9 c2 470nf-x2 r1 4 39k c3 680nf-x2 c6 470nf-630v c1 4 3.3uf c1 3 220nf d4 ll4148 c7 330uf-450v c1 0 33n +40 0vdc +40 0vdc 1-2 5-6 11 8 90 - 265vac 1 2 jp101 jumper 1 2 jp102 jumper inv comp mult cs vcc gd gnd zcd
package mechanical data L6562AT 21/25 9 package mechanical data in order to meet environmental requirements, st offers these de vices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions an d product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data L6562AT 22/25 figure 31. package dimensions table 7. dip-8 mechanical data dim. mm inch min typ max min typ max a 3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060
package mechanical data L6562AT 23/25 table 8. so-8 mechanical data dim. mm. inch min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 1. dimensions d does not include mold fl ash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm (.006inc h) in total (both side). 4.80 5.00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0 (min.), 8 (max.) ddd 0.10 0.004 figure 32. package dimensions
revision history L6562AT 24/25 10 revision history table 9. document revision history date revision changes 19-jan-2009 1 first release 04-mar-2009 2 updated table 5 on page 6
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